The present invention relates to memory systems, and more particularly, to memory architectures that allow multiple bits to be stored in each memory cell.
Dynamic random-access memories (DRAMs) provide the bulk of the semiconductor-based memories on most computer systems. A DRAM stores data in the form of charge that is stored on a capacitor within the memory cell. The current commercially available DRAMs store one bit in each memory cell, which consists of a transistor and a capacitor. The cost per bit stored is determined by the size of the memory cell. Hence, the prior art has achieved cost reductions in DRAMs by reducing the size of the transistor and capacitor.
A second method for reducing the cost of DRAM storage is to utilize memory cells that can store multiple bits per memory cell. To store N bits per memory cell, each memory cell must provide 2N discrete distinguishable states. In general, the states correspond to the charge stored on a capacitor. The maximum number of bits that can be stored depends on the sensitivity of the circuits used to measure the stored charge and on the ability of the write circuits to precisely control the amount of charge that is stored on the capacitor. Prior art multilevel DRAMS have been limited to two or three bits per storage cell.
The amount of charge that leaks off of the capacitor is a non-linear function of the amount of charge that was stored on the capacitor during programming. To compensate for the charge leakage, reference cells that are written at the same time as the storage cells are programmed with predetermined data values. Hence, the size of a xe2x80x9cwordxe2x80x9d that stores M bits of data must be increased by the number of reference cells needed to read the data in that word. At the time the data is read from the storage cells, it is compared to the values in the reference cells. If the number of storage levels is relatively small, a reference cell can be included for each possible data value. However, this strategy fails if the number of storage levels is high. For example, if each storage cell stores 8 bits, than each word would require 256 reference cells. Any savings realized by storing multiple bits per memory cell would be consumed by the additional reference cells. U.S. patent application Ser. No. 09/476,625, referenced above, describes a DRAM memory that utilizes reference cells to correct for charge leakage while keeping the number of reference cells to a reasonable number.
Multi-level EEPROM memories also suffer the leakage problems discussed above, but to a much lesser extent. In a multi-level EEPROM cell, data is stored by storing charge on a floating gate, the amount of charge stored controls the conductivity of the channel between the source and drain of a transistor. The number of different states that can be stored on a single transistor depends on the accuracy with which the charge level can be set and the accuracy with which the stored charge level can be read. While the leakage rate of charge from the floating gate is small, it is still significant enough to reduce the number of bits that can be stored in the transistor if corrections are not made for this leakage. U.S. patent application Ser. No. 09/417,040, referenced above, describes an EEPROM memory that utilizes reference cells to correct for charge leakage.
Broadly, it is the object of the present invention to provide an improved multilevel memory.
It is a further object of the present invention to provide a memory that does not require one reference cell per storage level.
These and other objects of the present invention will become apparent to those skilled in the art from the following detailed description of the invention and the accompanying drawings.
The present invention is a memory that includes a plurality of storage words, a data line, a plurality of reference lines, and a read circuit. Each storage word includes a data memory cell and a plurality of reference memory cells. Each memory cell includes an isolation transistor and a storage element having first and second terminals for storing a charge. The stored charge determines a conductivity value measurable between the first and second terminals. The isolation transistor is connected to the first terminal and connects the first terminal to one of the lines. The first terminal of the data memory cell is connected to the data line, and the first terminal of each of the reference memory cells is connected to a corresponding one of the reference lines when the isolation transistors are in a conducting state. The isolation transistors are placed in the conducting state by a signal on a word line connected to each of the isolation transistors in the storage word. The read circuit generating a digital value indicative of the value stored in the data memory cell of a storage word that is connected to the data and reference lines by comparing the conductivity of the data line with a continuous conductivity curve determined by the conductivities of the reference lines. In one embodiment of the invention, the conductivity curve is a piece-wise linear curve, having linear segments determined by the conductivities of the reference lines. Data is written into a storage word by a write circuit that causes a charge determined by an input digital value to be stored in the storage memory cell of one of the storage words. A charge determined by each of a plurality of predetermined reference values is also stored in a corresponding one of each of the reference memory cells. The present invention can utilize EEPROM or DRAM cells for the memory cells.